RTL Logic Design & IP Verification

JD for RTL Logic Design

Ø  Contribute to micro-architecture specification for ASIC/SoC design block

Ø  Participate in ASIC/SOC Chip Architecture specification reviews

Ø  Interact with ASIC/SOC integration, verification and physical design teams and also with IP vendors

Ø  Handle complete responsibility of an entire block starting from Micro-architecture specifications, RTL implementation, Linting, CDC, Synthesis/STA

Ø  Participated in 2-3 ASIC projects

Ø  Must have extensive experience in Micro-architecture design for ASIC/SoC sub-blocks

Ø  Extensive experience in ASIC RTL coding

Ø  Experience in low power design techniques

Ø  Good understanding of DFx design techniques

Ø  Good appreciation of AXI/AHB bus protocol, GigBE, USB,  NAND Flash Technology, PCIe Gen2/3 Host interface, DDR2/3 memory interfaces etc.

JD for IP Verification

Ø  Test case development, Review

Ø  Test case debugging (Debug independently, until root cause the issue)

Ø  Raise bugs and follow through the bug closure process in HSD until it is disposition

Ø  Feedback on test Plan

Ø  Development of Coverage Points & Review of coverage point to make sure 100% hit

Ø  Development, Review and debug assertion checker; checker failure being understood and make sure all failure clean at the end of project

Ø  Regression execution and result / failure analysis and initial-level debugging

Ø  Report Errors, Warning & send regression reports

Ø  Test Bench Creation, Modify and debug in UVM / SV language

Ø  Test Bench Issue Failure / Debug

Ø  Technical Project Management, and ownership of Project delivery related KPI

Ø  Guide and Train Engineers in Tools and Processes related to Verification

Ø  Participate in review, debug, project meetings

If you are eligible and interested, email your resume to r.rajaravi@gmail.com along with this drive details